# Reading D:/program/ALTERA/MODELSIM/modelsim_ase/tcl/vsim/pref.tcl 
# do DDS_run_msim_rtl_verilog.do 
# if {[file exists rtl_work]} {
# 	vdel -lib rtl_work -all
# }
# vlib rtl_work
# vmap work rtl_work
# Copying D:\program\ALTERA\MODELSIM\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini
# Modifying modelsim.ini
# ** Warning: Copied D:\program\ALTERA\MODELSIM\modelsim_ase\win32aloem/../modelsim.ini to modelsim.ini.
#          Updated modelsim.ini.
# 
# vlog -vlog01compat -work work +incdir+F:/QUARTUS_program/DDS_R092/DDS {F:/QUARTUS_program/DDS_R092/DDS/DDS.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module DDS
# 
# Top level modules:
# 	DDS
# vlog -vlog01compat -work work +incdir+F:/QUARTUS_program/DDS_R092/DDS {F:/QUARTUS_program/DDS_R092/DDS/sin_ROM.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module sin_ROM
# 
# Top level modules:
# 	sin_ROM
# vlog -vlog01compat -work work +incdir+F:/QUARTUS_program/DDS_R092/DDS {F:/QUARTUS_program/DDS_R092/DDS/Freq_sum.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module Freq_sum
# 
# Top level modules:
# 	Freq_sum
# vlog -vlog01compat -work work +incdir+F:/QUARTUS_program/DDS_R092/DDS {F:/QUARTUS_program/DDS_R092/DDS/phase_crtl.v}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module phase_crtl
# 
# Top level modules:
# 	phase_crtl
# 
# vlog -vlog01compat -work work +incdir+F:/QUARTUS_program/DDS_R092/DDS/simulation/modelsim {F:/QUARTUS_program/DDS_R092/DDS/simulation/modelsim/DDS.vt}
# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov  2 2012
# -- Compiling module DDS_vlg_tst
# 
# Top level modules:
# 	DDS_vlg_tst
# 
# vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneiii_ver -L rtl_work -L work -voptargs="+acc"  DDS_vlg_tst
# vsim -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneiii_ver -L rtl_work -L work -voptargs=\"+acc\" -t 1ps DDS_vlg_tst 
# Loading work.DDS_vlg_tst
# Loading work.DDS
# Loading work.sin_ROM
# Loading altera_mf_ver.altsyncram
# Loading altera_mf_ver.ALTERA_DEVICE_FAMILIES
# Loading altera_mf_ver.ALTERA_MF_MEMORY_INITIALIZATION
# Loading work.Freq_sum
# Loading work.phase_crtl
# 
# add wave *
# view structure
# .main_pane.structure.interior.cs.body.struct
# view signals
# .main_pane.objects.interior.cs.body.tree
# run -all
add wave -position insertpoint sim:/DDS_vlg_tst/i1/i_Freq_sum/*
restart
run
add wave -position insertpoint sim:/DDS_vlg_tst/i1/i_phase_crtl/*
restart
run
run
run
run
run
add wave -position insertpoint sim:/DDS_vlg_tst/i1/i_sin_ROM/*
restart
run
run
run
