16x16点阵显示汉字设计Verilog代码VIVADO仿真

名称：16x16点阵显示汉字设计Verilog代码VIVADO仿真

软件：VIVADO

语言：Verilog

代码功能：16x16点阵显示汉字

FPGA代码Verilog/VHDL代码资源下载：www.hdlcode.com

设计文档：

设计文档.doc

1. 点阵显示汉字

工程文件

程序文件

程序编译

Testbench

仿真图

字模软件介绍

部分代码展示:

//显示"张艺明"
module lattice_led(
input clk,//时钟
output reg [15:0] row,//点阵行信号
output reg [15:0] column  //列信号
);
reg [15:0] characters[47:0];
//汉字赋值
always@(posedge clk)
begin//汉字1--张
characters[0] <=16'h0900;
characters[1] <=16'hFD08;
characters[2] <=16'h0908;
characters[3] <=16'h0910;
characters[4] <=16'h0920;
characters[5] <=16'h7940;
characters[6] <=16'h4104;
characters[7] <=16'h47FE;
characters[8] <=16'h4140;
characters[9] <=16'h7940;
characters[10]<=16'h0920;
characters[11]<=16'h0920;
characters[12]<=16'h0910;
characters[13]<=16'h094E;
characters[14]<=16'h5184;
characters[15]<=16'h2100;
//汉字2--艺
characters[16]<=16'h0440;
characters[17]<=16'h0444;
characters[18]<=16'hFFFE;
characters[19]<=16'h0440;
characters[20]<=16'h0000;
characters[21]<=16'h3FC0;
characters[22]<=16'h0080;
characters[23]<=16'h0100;
characters[24]<=16'h0200;
characters[25]<=16'h0400;
characters[26]<=16'h0800;
characters[27]<=16'h1000;
characters[28]<=16'h2002;
characters[29]<=16'h2002;
characters[30]<=16'h2002;
characters[31]<=16'h1FFE;
//汉字3--明

代码文件（付费下载）：