Quartus电子拔河游戏VHDL代码开发板
名称:Quartus电子拔河游戏VHDL代码开发板
软件:Quartus
语言:VHDL
代码功能:
设计一个能进行拔河游戏的电路。电路使用15个(或9个)发光二极管表示拔河的“电子绳”,开机后只有中间一个发亮,此即拔河的中心点。游戏甲乙双方各持一个按钮,迅速地、不断地按动产生脉冲,谁按得快,亮点向谁方向移动,每按一次,亮点移动次。亮点移到任一方终端二极管,这一方就获胜,此时双方按钮均无作用,输出保持,只有复位后才使亮点恢复到中心
由裁判下达比赛开始命令后,甲乙双方才能输入信号,否则输入信号无效 用数码管显示获胜者的盘数,每次比赛结束自动给获胜方加分
FPGA代码Verilog/VHDL代码资源下载:www.hdlcode.com
本代码已在开发板验证,开发板如下,其他开发板可以修改管脚适配:
演示视频:
设计文档:
1. 工程文件

2. 程序文件



3. 程序编译

4. RTL图

状态图

5. 管脚分配

6. 仿真图


部分代码展示:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
--控制模块
ENTITY bahe_ctrl IS
PORT (
clk : IN STD_LOGIC;--标准时钟
reset_n : IN STD_LOGIC;--复位信号,低有效
reset_cnt : IN STD_LOGIC;--计数复位信号,低有效
shift1 : IN STD_LOGIC;--选手1
shift2 : IN STD_LOGIC;--选手2
led : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);--7个led
led_flash : OUT STD_LOGIC;
win1_times :OUT STD_LOGIC_VECTOR(15 DOWNTO 0);--1号获胜次数
win2_times :OUT STD_LOGIC_VECTOR(15 DOWNTO 0)--2号获胜次数
);
END bahe_ctrl;
ARCHITECTURE behave OF bahe_ctrl IS
TYPE State_type IS (s_idle, s_start, s_left_shift, s_right_shift, s_win_1, s_win_2); -- 定义状态
SIGNAL state : State_Type; -- 创建信号
SIGNAL game_led : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0001000";
SIGNAL win1_num : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0000000000000000";
SIGNAL win2_num : STD_LOGIC_VECTOR(15 DOWNTO 0) := "0000000000000000";
SIGNAL cnt1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := "00000000000000000000000000000000";
SIGNAL clk1 : STD_LOGIC := '0';
BEGIN
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF ((NOT(reset_n)) = '1') THEN
state <= s_idle;
ELSE
CASE state IS
WHEN s_idle =>--复位状态
state <= s_start;
WHEN s_start =>--游戏中
IF (game_led = "1000000") THEN
state <= s_win_1;--1号赢
ELSIF (game_led = "0000001") THEN
state <= s_win_2;--2号赢
ELSIF (shift1 = '1') THEN
state <= s_left_shift;--led左移
ELSIF (shift2 = '1') THEN
state <= s_right_shift;--led右移
ELSE
state <= s_start;
END IF;
WHEN s_left_shift =>--led左移
state <= s_start;
WHEN s_right_shift =>--led右移
state <= s_start;
WHEN s_win_1 =>
state <= s_win_1;--1号赢
WHEN s_win_2 =>
state <= s_win_2;--2号赢
WHEN OTHERS =>
END CASE;
END IF;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF ((NOT(reset_n)) = '1') THEN--复位
game_led <= "0001000";
ELSIF (state = s_left_shift) THEN
game_led <= (game_led(5 DOWNTO 0) & '0');--led左移
ELSIF (state = s_right_shift) THEN
game_led <= ('0' & game_led(6 DOWNTO 1));--led右移
END IF;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF ((NOT(reset_cnt)) = '1') THEN--复位
win1_num <= "0000000000000000";
ELSIF (state = s_start and game_led = "1000000") THEN----1号赢
win1_num <=win1_num+ "0000000000000001";--加1
ELSE
win1_num <=win1_num;
END IF;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF ((NOT(reset_cnt)) = '1') THEN--复位
win2_num <= "0000000000000000";
ELSIF (state = s_start and game_led = "0000001") THEN----2号赢
win2_num <=win2_num+ "0000000000000001";--加1
ELSE
win2_num <=win2_num;
END IF;
END IF;
END PROCESS;
PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF (cnt1 >= "00000000001111010000100100000000") THEN
cnt1 <= "00000000000000000000000000000000";
clk1 <= NOT(clk1);
ELSE
cnt1 <= cnt1 + "00000000000000000000000000000001";
END IF;
END IF;
END PROCESS;
--输出
win1_times<=win1_num;
win2_times<=win2_num;
led <= game_led;
led_flash<=clk1;
END behave;代码文件(付费下载):
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3、优质Verilog/VHDL代码资源,所见即所得。
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